A PPL Based 32MHz ~ 1GHz Wide Band Clock Generator Circuit for High Speed Microprocessors 


Vol. 7,  No. 1, pp. 235-244, Jan.  2000
10.3745/KIPSTE.2000.7.1.235


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  Abstract

This paper presents a low power PLL based clock generator circuit for microprocessors. It generates 32MHz~1GHz clocks and can be intergrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characterisrics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage conrolled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1GHz. The clock generator is designed by using 0.65㎛ CMOS full custom technology and operates with 1.1㎲ lock-in time. The power consumption is less than 20mW.

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[IEEE Style]

S. K. Kim, J. H. Lee, S. H. Lee, K. M. Chung, "A PPL Based 32MHz ~ 1GHz Wide Band Clock Generator Circuit for High Speed Microprocessors," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 1, pp. 235-244, 2000. DOI: 10.3745/KIPSTE.2000.7.1.235.

[ACM Style]

Sang Kyu Kim, Jae Hyung Lee, Soo Hyung Lee, and Kang Min Chung. 2000. A PPL Based 32MHz ~ 1GHz Wide Band Clock Generator Circuit for High Speed Microprocessors. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 1, (2000), 235-244. DOI: 10.3745/KIPSTE.2000.7.1.235.

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