A Dual Slotted Ring Organization for Reducing Memory Access Latency in Distributed Shared Memory System 


Vol. 8,  No. 4, pp. 419-428, Dec.  2001
10.3745/KIPSTA.2001.8.4.419


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  Abstract

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

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[IEEE Style]

J. S. Min and T. M. Chang, "A Dual Slotted Ring Organization for Reducing Memory Access Latency in Distributed Shared Memory System," The KIPS Transactions:PartA, vol. 8, no. 4, pp. 419-428, 2001. DOI: 10.3745/KIPSTA.2001.8.4.419.

[ACM Style]

Jun Sik Min and Tae Mu Chang. 2001. A Dual Slotted Ring Organization for Reducing Memory Access Latency in Distributed Shared Memory System. The KIPS Transactions:PartA, 8, 4, (2001), 419-428. DOI: 10.3745/KIPSTA.2001.8.4.419.

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