A Design and Implementation of a Timing Analysis Simulator for a Design Space Exploration on a Hybrid Embedded System 


Vol. 9,  No. 4, pp. 459-466, Dec.  2002
10.3745/KIPSTA.2002.9.4.459


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  Abstract

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAs to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DSE, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

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[IEEE Style]

S. Y. Ahn, J. H. Shim, J. A. Lee, "A Design and Implementation of a Timing Analysis Simulator for a Design Space Exploration on a Hybrid Embedded System," The KIPS Transactions:PartA, vol. 9, no. 4, pp. 459-466, 2002. DOI: 10.3745/KIPSTA.2002.9.4.459.

[ACM Style]

Seong Yong Ahn, Jea Hong Shim, and Jeong A Lee. 2002. A Design and Implementation of a Timing Analysis Simulator for a Design Space Exploration on a Hybrid Embedded System. The KIPS Transactions:PartA, 9, 4, (2002), 459-466. DOI: 10.3745/KIPSTA.2002.9.4.459.

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