Bit-Parallel Systolic Divider in Finite Field GF(2m) 


Vol. 11,  No. 2, pp. 109-114, Apr.  2004
10.3745/KIPSTA.2004.11.2.109


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  Abstract

This paper presents a high-speed bit-parallel systolic divider for computing modular division A(x)/B(x) mod G(x) in finite fields GF(2m). The presented divider is based on the binary GCD algorithm and 5m-2. through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition,since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity,it provides a high flexibility and scalability with respect to the field size m. Therefore,the proposed divider is well suited to VLSI implementation.

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[IEEE Style]

K. C. Hun, K. J. Jin, A. B. Gyu, H. C. Pyo, "Bit-Parallel Systolic Divider in Finite Field GF(2m)," The KIPS Transactions:PartA, vol. 11, no. 2, pp. 109-114, 2004. DOI: 10.3745/KIPSTA.2004.11.2.109.

[ACM Style]

Kim Chang Hun, Kim Jong Jin, An Byeong Gyu, and Hong Chun Pyo. 2004. Bit-Parallel Systolic Divider in Finite Field GF(2m). The KIPS Transactions:PartA, 11, 2, (2004), 109-114. DOI: 10.3745/KIPSTA.2004.11.2.109.

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