Design and Performance Evaluation of Expansion Buffer Cache 


Vol. 11,  No. 7, pp. 489-498, Dec.  2004
10.3745/KIPSTA.2004.11.7.489


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  Abstract

VLIW processor is considered to be an appropriate processor for the embedded system, provided with high performance and low power consumption due to its simple hardware structure. Unfortunately, the VLIW processor often suffers from high memory access latency due to the variable length of I-packets, which consist of independent instructions to be issued in parallel. It is because of the variable I-packet length that some I-packets must be placed over two cache blocks, which are called straddle I-packets, so that two cache accesses are required to fecth such I-packets. In this paper, an expansion buffer cache is proposed to improve not only the imstruction fetch bandwidth, but also the power consumption of the I-cache with moderate hardware cost. The expansion buffer cache has a small expantion buffer containing a fraction of a straddle packet along with the main cache to reduce the additional cache accesses due to the straddle I-packets. With a great reduction in the cache accesses due to the straddle packets, the expansion buffer cache can achieve 5~19% improvement over the conventional I-caches in the Delay, Power, Area metric.

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[IEEE Style]

W. K. Hong, "Design and Performance Evaluation of Expansion Buffer Cache," The KIPS Transactions:PartA, vol. 11, no. 7, pp. 489-498, 2004. DOI: 10.3745/KIPSTA.2004.11.7.489.

[ACM Style]

Won Kee Hong. 2004. Design and Performance Evaluation of Expansion Buffer Cache. The KIPS Transactions:PartA, 11, 7, (2004), 489-498. DOI: 10.3745/KIPSTA.2004.11.7.489.

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