A Level One Cache Organization for Chip-Size Limited Single Processor 


Vol. 12,  No. 2, pp. 127-136, Apr.  2005
10.3745/KIPSTA.2005.12.2.127


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  Abstract

This paper measured a proper ratio of the size of demand fetch cache L1 to that of prefetch cache Lp by imulation when the size of L1 and Lp are constant which organize space-limited level 1 cache of a single microprocessor chip. The analysis of our experiment showed that in the condition of the sum of the size of L1 and Lp are 16 KB, the level 1 cache organization by constituting Lp with 4 KB and employing OBL, and FIFO as a prefetch technique and a cache replacement policy respectively resulted in the best performance. Also, this analysis showed that in the condition of the sum of the size of L1 and Lp are over 32 KB and, employing dynamic filtering as prefetch technique of Lp are more advantageous and splitting level 1 cache by constituting L1 with 28 KB and Lp with 4 KB in the case of 32 KB of space are available, by constituting L1 with 48 KB and Lp with 16 KB in the case of 64 KB elicited the best performance.

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[IEEE Style]

Y. K. Ju and S. I. Kim, "A Level One Cache Organization for Chip-Size Limited Single Processor," The KIPS Transactions:PartA, vol. 12, no. 2, pp. 127-136, 2005. DOI: 10.3745/KIPSTA.2005.12.2.127.

[ACM Style]

Young Kwan Ju and Suk Il Kim. 2005. A Level One Cache Organization for Chip-Size Limited Single Processor. The KIPS Transactions:PartA, 12, 2, (2005), 127-136. DOI: 10.3745/KIPSTA.2005.12.2.127.

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