Computer Graphics & Efficient Simulation Acceleration by FPGA Compilation Avoidance 


Vol. 14,  No. 3, pp. 141-146, Jun.  2007
10.3745/KIPSTA.2007.14.3.141


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  Abstract

In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

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[IEEE Style]

K. H. Shim, C. H. Park, S. Y. Yang, "Computer Graphics & Efficient Simulation Acceleration by FPGA Compilation Avoidance," The KIPS Transactions:PartA, vol. 14, no. 3, pp. 141-146, 2007. DOI: 10.3745/KIPSTA.2007.14.3.141.

[ACM Style]

Kyu Ho Shim, Chang Ho Park, and Sei Yang Yang. 2007. Computer Graphics & Efficient Simulation Acceleration by FPGA Compilation Avoidance. The KIPS Transactions:PartA, 14, 3, (2007), 141-146. DOI: 10.3745/KIPSTA.2007.14.3.141.

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