High Performance Coprocessor Architecture for Real-Time Dense Disparity Map 


Vol. 14,  No. 5, pp. 301-308, Oct.  2007
10.3745/KIPSTA.2007.14.5.301


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  Abstract

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation (LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD (Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

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  Cite this article

[IEEE Style]

C. G. Kim and S. D. Kim, "High Performance Coprocessor Architecture for Real-Time Dense Disparity Map," The KIPS Transactions:PartA, vol. 14, no. 5, pp. 301-308, 2007. DOI: 10.3745/KIPSTA.2007.14.5.301.

[ACM Style]

Cheong Ghil Kim and Shin Dug Kim. 2007. High Performance Coprocessor Architecture for Real-Time Dense Disparity Map. The KIPS Transactions:PartA, 14, 5, (2007), 301-308. DOI: 10.3745/KIPSTA.2007.14.5.301.

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