Low Power Mapping Algorithm Considering Data Transfer Time for CGRA 


Vol. 19,  No. 1, pp. 17-22, Feb.  2012
10.3745/KIPSTA.2012.19.1.17


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  Abstract

The demand of high performance processor is soaring due to the extending of mobile and small electronic device market. CGRA(Coarse Grained Reconfigurable Architecture) is the processor satisfying both of performance and low-power demands and a great alternative of ASIC that can be reconfigured. This paper presents a novel low-power mapping algorithm that optimizes the number of used computation resource in the mapping phase by considering data transfer time. Compared with previous mapping algorithm, ours reduce energy consumption by up to 73%, and 56.4% on average.

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[IEEE Style]

Y. J. Kim, J. H. Youn, D. S. Cho, Y. H. Paek, "Low Power Mapping Algorithm Considering Data Transfer Time for CGRA," The KIPS Transactions:PartA, vol. 19, no. 1, pp. 17-22, 2012. DOI: 10.3745/KIPSTA.2012.19.1.17.

[ACM Style]

Yong Joo Kim, Jong Hee Youn, Doo San Cho, and Yun Heung Paek. 2012. Low Power Mapping Algorithm Considering Data Transfer Time for CGRA. The KIPS Transactions:PartA, 19, 1, (2012), 17-22. DOI: 10.3745/KIPSTA.2012.19.1.17.

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