Register Pressure Aware Code Selection Algorithm for Multi-Output Instructions 


Vol. 19,  No. 1, pp. 45-50, Feb.  2012
10.3745/KIPSTA.2012.19.1.45


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  Abstract

The demand for faster execution time and lower energy consumption has compelled architects of embedded processors to customize it to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a multi-output instruction (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However the earlier algorithm does not consider the register pressure. So, some selected MOIs introduce register spill/reload code that increases the code size and instruction count. To attack this problem, we introduce a novel iterated instruction selection algorithm based on the register pressure of each selected MOIs. The experimental results show the suggested algorithm achieves 3% code-size reduction and 2.7% speed-up on average.

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[IEEE Style]

J. H. Youn, Y. H. Paek, K. M. Ko, "Register Pressure Aware Code Selection Algorithm for Multi-Output Instructions," The KIPS Transactions:PartA, vol. 19, no. 1, pp. 45-50, 2012. DOI: 10.3745/KIPSTA.2012.19.1.45.

[ACM Style]

Jong Hee Youn, Yun Heung Paek, and Kwang Man Ko. 2012. Register Pressure Aware Code Selection Algorithm for Multi-Output Instructions. The KIPS Transactions:PartA, 19, 1, (2012), 45-50. DOI: 10.3745/KIPSTA.2012.19.1.45.

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