An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing 


Vol. 13,  No. 3, pp. 223-230, Jun.  2006
10.3745/KIPSTB.2006.13.3.223


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  Abstract

A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform all of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA (Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.

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[IEEE Style]

S. H. Jin, J. U. Cho, K. H. Kwon, J. W. Jeon, "An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing," The KIPS Transactions:PartB , vol. 13, no. 3, pp. 223-230, 2006. DOI: 10.3745/KIPSTB.2006.13.3.223.

[ACM Style]

S. H. Jin, J. U. Cho, K. H. Kwon, and J. W. Jeon. 2006. An FPGA Implementation of Parallel Hardware Architecture for the Real-time Window-based Image Processing. The KIPS Transactions:PartB , 13, 3, (2006), 223-230. DOI: 10.3745/KIPSTB.2006.13.3.223.

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