A Gigabit Rate Packet Header Collector using Network Processor 


Vol. 12,  No. 1, pp. 11-18, Feb.  2005
10.3745/KIPSTC.2005.12.1.11


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  Abstract

This paper proposes a packet header collector, based on a network processor with multi-threads, that shows a high throughput on gigabit network. The proposed collector has an architecture to separate packets coming from gigabit network into headers and payloads, and distribute them to multiple 100Mbit MAC ports. The architecture hiring a unique buffer management method and load distribution strategy among multiple processors is evaluated empirically in depth.

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[IEEE Style]

P. A. Choi, K. H. Choi, G. H. Jung, J. H. Sim, "A Gigabit Rate Packet Header Collector using Network Processor," The KIPS Transactions:PartC, vol. 12, no. 1, pp. 11-18, 2005. DOI: 10.3745/KIPSTC.2005.12.1.11.

[ACM Style]

Pan An Choi, Kyung Hee Choi, Gi Hyun Jung, and Jae Hong Sim. 2005. A Gigabit Rate Packet Header Collector using Network Processor. The KIPS Transactions:PartC, 12, 1, (2005), 11-18. DOI: 10.3745/KIPSTC.2005.12.1.11.

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