An Implementation of the Fault Simulator for Switch Level Faults 


Vol. 4,  No. 2, pp. 628-637, Feb.  1997
10.3745/KIPSTE.1997.4.2.628


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  Abstract

This paper describes an implementation of fault simulator that can handle switch level fault models such as transistor stuck-open and stuck-closed faults as well as stuck-at fault. It overcomes the limitations when only stuck-at faults are used in VLSI circuits. Signal flow of a transistor switch is bidirectional in its nature, but most of signal flows in a switch level circuits, about 95%, are in one direction. This fault simulator focuses on the way which changes a switch level circuit into a graph model with two directed edges. Two paths from Vdd to ground and from ground to Vdd are the two directions. Logic simulation is performed along dominant signal flows. The switch level fault simulation estimates the dominant path by infecting switch-level faults, and two pattern vectors are used for fault simulation. Experimental results are shown to demonstrate correctnesss of the fault simulator.

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[IEEE Style]

Y. Y. Mo and M. H. Bok, "An Implementation of the Fault Simulator for Switch Level Faults," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 2, pp. 628-637, 1997. DOI: 10.3745/KIPSTE.1997.4.2.628.

[ACM Style]

Yeon Yun Mo and Min Hyoung Bok. 1997. An Implementation of the Fault Simulator for Switch Level Faults. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 2, (1997), 628-637. DOI: 10.3745/KIPSTE.1997.4.2.628.

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