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Design of a Low-Power MOS Current-Mode Logic Circuit
Jeong Beom Kim
Vol. 17, No. 3, pp. 121-126, Jun. 2010
10.3745/KIPSTA.2010.17.3.121
Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS
Dong Hwi Kim   Jeong Beom Kim
Vol. 15, No. 5, pp. 243-248, Oct. 2008
10.3745/KIPSTA.2008.15.5.243
Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic
Jeong Beom Kim
Vol. 15, No. 3, pp. 135-140, Jun. 2008
10.3745/KIPSTA.2008.15.3.135
Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor
Jeong Beom Kim
Vol. 15, No. 2, pp. 69-74, Apr. 2008
10.3745/KIPSTA.2008.15.2.69
Computer Graphics & Design of a 64x64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits
Jeong Beom Kim
Vol. 14, No. 4, pp. 203-208, Aug. 2007
10.3745/KIPSTA.2007.14.4.203
Computer Graphics & Design of a Low-Power Parallel Multiplier Using Low-Swing Technique
Jeong Beom Kim
Vol. 14, No. 3, pp. 147-150, Jun. 2007
10.3745/KIPSTA.2007.14.3.147
Efficient Session Management mechanism applied Key Recovery technique in IPSec
Jeong Beom Kim  Yun Jung Rhee  Nam Sup Park  Tai Yun Kim
Vol. 8, No. 6, pp. 775-782, Dec. 2001
10.3745/KIPSTC.2001.8.6.775

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