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A Buffer Architecture based on Dynamic Mapping table for Write Performance of Solid State Disk
In Pyo Cho So Hyang Ko Hoon Mo Yang Gi Ho Park Shin Dug Kim
Vol. 18, No. 4, pp. 135-142, Aug. 2011
10.3745/KIPSTA.2011.18.4.135
Vol. 18, No. 4, pp. 135-142, Aug. 2011

An Efficient Cache Mechanism for Improving Response Times in Integrated RFID Middleware
Cheong Ghil Kim Jun Hwan Lee Kyung Lang Park Shin Dug Kim
Vol. 15, No. 1, pp. 17-26, Feb. 2008
10.3745/KIPSTA.2008.15.1.17
Vol. 15, No. 1, pp. 17-26, Feb. 2008

A Real-time Single-Pass Visibility Culling Method Based on a 3D Graphics Accelerator Architecture
Catherine Choo Moon Hee Choi Shin Dug Kim
Vol. 15, No. 1, pp. 1-8, Feb. 2008
10.3745/KIPSTA.2008.15.1.1
Vol. 15, No. 1, pp. 1-8, Feb. 2008

Low-Power Data Cache Architecture and Microarchitecture-Level Management Policy for Multimedia Application
Hoon Mo Yang Cheong Gil Kim Gi Ho Park Shin Dug Kim
Vol. 13, No. 3, pp. 191-198, Jun. 2006
10.3745/KIPSTA.2006.13.3.191
Vol. 13, No. 3, pp. 191-198, Jun. 2006

The Design of Geometry Processor for 3D Graphics
Cheol Ho Jeong Woo Chan Park Shin Dug Kim Tack Don Han
Vol. 7, No. 1, pp. 252-265, Jan. 2000
10.3745/KIPSTE.2000.7.1.252
Vol. 7, No. 1, pp. 252-265, Jan. 2000

Design and Analysis of User's Libraries for Parallel Computing based on the Internet
Pil Sup Shin Chun Mok Chung Hye Seon Maeng Won Kee Hong Shin Dug Kim
Vol. 6, No. 11, pp. 2932-2945, Nov. 1999
10.3745/KIPSTE.1999.6.11.2932
Vol. 6, No. 11, pp. 2932-2945, Nov. 1999
