TY  - JOUR
T1  - Performance Evaluation and Consideration of 
Shadow Stack on RISC-V Architecture
AU  - Young, Kang Ha 
AU  - Won, Han Go 
AU  - Hwan, Park Sung 
AU  - Hyun, Kwon Dong 
JO  - The Transactions of the Korea Information Processing Society
PY  - 2024
DA  - 2024/2/28
DO  - https://doi.org/10.3745/TKIPS.2024.13.9.413
KW  - RISC-V
KW  - Shadow Stack
KW  - Security
AB  - RISC-V is an open-source instruction set architecture, used in various hardware implementations, and can be flexibly expanded to 
meet system requirements through the RV64I base instruction set and 16 standard extensions. Currently, the RISC-V architecture employs 
the shadow stack technique to protect return addresses. This paper compares the performance of the compact shadow stack mechanism 
and the parallel shadow stack mechanism in the RISC-V architecture using the SPEC CPU 2017 and beebs benchmarks. Experimental 
results show that the parallel shadow stack mechanism exhibits higher overhead than the compact shadow stack mechanism. This suggests 
that the efficiency of the parallel mechanism is reduced due to the limitations of the RISC-V architecture, making the compact shadow 
stack more suitable for RISC-V. Additionally, this paper identifies the security limitations of the existing RISC-V shadow stack and proposes 
directions for enhancing the performance and security of shadow stack mechanisms to ensure a secure execution environment for RISC-V.