Design and Implementation of Performance Monitor on Highly Parallel Computer 


Vol. 5,  No. 9, pp. 2421-2434, Sep.  1998
10.3745/KIPSTE.1998.5.9.2421


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  Abstract

This paper describes the design and implementation of performance monitor which can be used at SPAX that is developed to TICOM IV. SPAX has a hierarchical structure, at which nodes which have a local memory, are connected to interconnect network and constructed to clusters. So, to do effective performance monitoring at SPAX, new performance monitor is required, which is designed to consider the structure of SPAX. Implemented performance monitor is designed, which can monitor the state of node, cluster, and total system of SPAX.

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[IEEE Style]

K. D. Hyung and K. C. Kyu, "Design and Implementation of Performance Monitor on Highly Parallel Computer," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 9, pp. 2421-2434, 1998. DOI: 10.3745/KIPSTE.1998.5.9.2421.

[ACM Style]

Kim Do Hyung and Kim Chae Kyu. 1998. Design and Implementation of Performance Monitor on Highly Parallel Computer. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 9, (1998), 2421-2434. DOI: 10.3745/KIPSTE.1998.5.9.2421.

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