Computer Graphics & Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes 


Vol. 6,  No. 8, pp. 2204-2212, Aug.  1999
10.3745/KIPSTE.1999.6.8.2204


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  Abstract

In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial and error in the circuit design.

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[IEEE Style]

O. J. Wook and H. C. Ho, "Computer Graphics & Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 6, no. 8, pp. 2204-2212, 1999. DOI: 10.3745/KIPSTE.1999.6.8.2204.

[ACM Style]

Oh Jang Wook and Han Chang Ho. 1999. Computer Graphics & Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 6, 8, (1999), 2204-2212. DOI: 10.3745/KIPSTE.1999.6.8.2204.

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