Design and Performance Analysis of A TMS320C67x-based Parallel Signal Processing System 


Vol. 7,  No. 1, pp. 65-73, Jan.  2000
10.3745/KIPSTE.2000.7.1.65


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  Abstract

This paper deals with a design and performance analysis of a parallel signal processing system based on TMS320C67x. With an emphasis on the board-level design of the processor unit four models are proposed with different memory configurations and internal bus schemes. Several approaches to parallel processing of 2D FFT are also presented to be used for performance analysis. The performance of four board models are estimated and compared in terms of the time spent for local memory access, inter-processor communication, and inter-board communication. The results of performance analysis show that, when performance and implementation complexity are taken into account, the model with both local and shared memories is the most desirable.

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[IEEE Style]

B. P. Moon, J. S. Park, C. H. Jeon, S. J. Park, D. H. Lee, K. T. Han, "Design and Performance Analysis of A TMS320C67x-based Parallel Signal Processing System," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 7, no. 1, pp. 65-73, 2000. DOI: 10.3745/KIPSTE.2000.7.1.65.

[ACM Style]

Byung Pyo Moon, Joon Seok Park, Chang Ho Jeon, Sung Joo Park, Dong Ho Lee, and Ki Taek Han. 2000. Design and Performance Analysis of A TMS320C67x-based Parallel Signal Processing System. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 7, 1, (2000), 65-73. DOI: 10.3745/KIPSTE.2000.7.1.65.

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