Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure
Vol. 10, No. 4, pp. 279-284, Oct. 2003
10.3745/KIPSTA.2003.10.4.279
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[IEEE Style]
P. T. Geun and J. G. Won, "Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure," The KIPS Transactions:PartA, vol. 10, no. 4, pp. 279-284, 2003. DOI: 10.3745/KIPSTA.2003.10.4.279.
[ACM Style]
Park Tae Geun and Jo Gwang Won. 2003. Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure. The KIPS Transactions:PartA, 10, 4, (2003), 279-284. DOI: 10.3745/KIPSTA.2003.10.4.279.