Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure 


Vol. 10,  No. 4, pp. 279-284, Oct.  2003
10.3745/KIPSTA.2003.10.4.279


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  Abstract

In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery´s algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n 2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n 2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

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  Cite this article

[IEEE Style]

P. T. Geun and J. G. Won, "Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure," The KIPS Transactions:PartA, vol. 10, no. 4, pp. 279-284, 2003. DOI: 10.3745/KIPSTA.2003.10.4.279.

[ACM Style]

Park Tae Geun and Jo Gwang Won. 2003. Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure. The KIPS Transactions:PartA, 10, 4, (2003), 279-284. DOI: 10.3745/KIPSTA.2003.10.4.279.