An Area Efficient Low Power Data Cache for Multimedia Embedded Systems 


Vol. 13,  No. 2, pp. 101-110, Apr.  2006
10.3745/KIPSTA.2006.13.2.101


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  Abstract

One of the most effective ways to improve cache performance is to exploit both temporal and spatial locality given by any program executional characteristics. This paper proposes a data cache with small space for low power but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size and a fully-associative buffer with large block size. To overcome the disadvantage of small cache space, two mechanisms are enhanced by considering operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes and an efficient block filtering to remove rarely reused data. The simulations on MediaBench show that the proposed 5KB-cache can provide equivalent performance and reduce energy consumption up to 40% as compared with 16KB 4-way set associative cache.

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[IEEE Style]

C. G. Kim and S. D. Kim, "An Area Efficient Low Power Data Cache for Multimedia Embedded Systems," The KIPS Transactions:PartA, vol. 13, no. 2, pp. 101-110, 2006. DOI: 10.3745/KIPSTA.2006.13.2.101.

[ACM Style]

Cheong Ghil Kim and Shin Dug Kim. 2006. An Area Efficient Low Power Data Cache for Multimedia Embedded Systems. The KIPS Transactions:PartA, 13, 2, (2006), 101-110. DOI: 10.3745/KIPSTA.2006.13.2.101.

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