Design of a Parallel Rendering Processor Architecture with Effective Memory System
Vol. 13, No. 4, pp. 305-316, Aug. 2006
10.3745/KIPSTA.2006.13.4.305
Abstract
Statistics
|
Cite this article
[IEEE Style]
W. C. Park, D. K. Yoon, K. S. Kim, "Design of a Parallel Rendering Processor Architecture with Effective Memory System," The KIPS Transactions:PartA, vol. 13, no. 4, pp. 305-316, 2006. DOI: 10.3745/KIPSTA.2006.13.4.305.
[ACM Style]
Woo Chan Park, Duk Ki Yoon, and Kyoung Su Kim. 2006. Design of a Parallel Rendering Processor Architecture with Effective Memory System. The KIPS Transactions:PartA, 13, 4, (2006), 305-316. DOI: 10.3745/KIPSTA.2006.13.4.305.