Computer Graphics & Design of a Low-Power Parallel Multiplier Using Low-Swing Technique 


Vol. 14,  No. 3, pp. 147-150, Jun.  2007
10.3745/KIPSTA.2007.14.3.147


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  Abstract

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16×16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35㎛ standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

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[IEEE Style]

J. B. Kim, "Computer Graphics & Design of a Low-Power Parallel Multiplier Using Low-Swing Technique," The KIPS Transactions:PartA, vol. 14, no. 3, pp. 147-150, 2007. DOI: 10.3745/KIPSTA.2007.14.3.147.

[ACM Style]

Jeong Beom Kim. 2007. Computer Graphics & Design of a Low-Power Parallel Multiplier Using Low-Swing Technique. The KIPS Transactions:PartA, 14, 3, (2007), 147-150. DOI: 10.3745/KIPSTA.2007.14.3.147.

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