Computer Graphics & Design of a 64x64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits 


Vol. 14,  No. 4, pp. 203-208, Aug.  2007
10.3745/KIPSTA.2007.14.4.203


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  Abstract

This paper proposes a 64×64 Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung 0.35㎛ standard CMOS process at a 3.3V supply voltage and unit current 5㎂. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of 7.5×9.4 mm2, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

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[IEEE Style]

J. B. Kim, "Computer Graphics & Design of a 64x64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits," The KIPS Transactions:PartA, vol. 14, no. 4, pp. 203-208, 2007. DOI: 10.3745/KIPSTA.2007.14.4.203.

[ACM Style]

Jeong Beom Kim. 2007. Computer Graphics & Design of a 64x64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits. The KIPS Transactions:PartA, 14, 4, (2007), 203-208. DOI: 10.3745/KIPSTA.2007.14.4.203.

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