Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor 


Vol. 15,  No. 2, pp. 69-74, Apr.  2008
10.3745/KIPSTA.2008.15.2.69


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  Abstract

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16 x16 bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung 0.35 ㎛CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

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[IEEE Style]

J. B. Kim, "Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor," The KIPS Transactions:PartA, vol. 15, no. 2, pp. 69-74, 2008. DOI: 10.3745/KIPSTA.2008.15.2.69.

[ACM Style]

Jeong Beom Kim. 2008. Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor. The KIPS Transactions:PartA, 15, 2, (2008), 69-74. DOI: 10.3745/KIPSTA.2008.15.2.69.

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