Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic
Vol. 15, No. 3, pp. 135-140, Jun. 2008
10.3745/KIPSTA.2008.15.3.135
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[IEEE Style]
J. B. Kim, "Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic," The KIPS Transactions:PartA, vol. 15, no. 3, pp. 135-140, 2008. DOI: 10.3745/KIPSTA.2008.15.3.135.
[ACM Style]
Jeong Beom Kim. 2008. Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic. The KIPS Transactions:PartA, 15, 3, (2008), 135-140. DOI: 10.3745/KIPSTA.2008.15.3.135.