A Digit Serial Multiplier Over GF(2(m)) Based on the MSD-first Algorithm 


Vol. 15,  No. 3, pp. 161-166, Jun.  2008
10.3745/KIPSTA.2008.15.3.161


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  Abstract

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every clock cycles, where is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to . Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to . Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

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[IEEE Style]

H. K. Chang and S. C. Kim, "A Digit Serial Multiplier Over GF(2(m)) Based on the MSD-first Algorithm," The KIPS Transactions:PartA, vol. 15, no. 3, pp. 161-166, 2008. DOI: 10.3745/KIPSTA.2008.15.3.161.

[ACM Style]

Hoon Kim Chang and Soon Cheol Kim. 2008. A Digit Serial Multiplier Over GF(2(m)) Based on the MSD-first Algorithm. The KIPS Transactions:PartA, 15, 3, (2008), 161-166. DOI: 10.3745/KIPSTA.2008.15.3.161.

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