Design of a Low-Power MOS Current-Mode Logic Circuit 


Vol. 17,  No. 3, pp. 121-126, Jun.  2010
10.3745/KIPSTA.2010.17.3.121


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  Abstract

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The 16x16 bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung 0.18 ㎛ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

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[IEEE Style]

J. B. Kim, "Design of a Low-Power MOS Current-Mode Logic Circuit," The KIPS Transactions:PartA, vol. 17, no. 3, pp. 121-126, 2010. DOI: 10.3745/KIPSTA.2010.17.3.121.

[ACM Style]

Jeong Beom Kim. 2010. Design of a Low-Power MOS Current-Mode Logic Circuit. The KIPS Transactions:PartA, 17, 3, (2010), 121-126. DOI: 10.3745/KIPSTA.2010.17.3.121.

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