An Efficient Record-Replay Mechanism using Hardware Performance Counters and Debugging Facilities 


Vol. 18,  No. 5, pp. 177-180, Oct.  2011
10.3745/KIPSTA.2011.18.5.177


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  Abstract

In this paper, we present a record-replay technique based on interrupt logging and reproduction. Race conditions have been considered as the main source of nondeterminism in conventional record-replay approaches. However, interrupts are another source of nondeterministic computer system behavior, which must be reproduced at accurate time points, let alone the order of interrupt occurrence. We show that an interrupt-based replayer can be efficiently and effectively implemented by using hardware performance counters and debugging functionality. Experiments also show that the runtime overhead of the interrupt-based replayer is sufficiently low.

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[IEEE Style]

J. C. Maeng and M. S. Ryu, "An Efficient Record-Replay Mechanism using Hardware Performance Counters and Debugging Facilities," The KIPS Transactions:PartA, vol. 18, no. 5, pp. 177-180, 2011. DOI: 10.3745/KIPSTA.2011.18.5.177.

[ACM Style]

Ji Chan Maeng and Min Soo Ryu. 2011. An Efficient Record-Replay Mechanism using Hardware Performance Counters and Debugging Facilities. The KIPS Transactions:PartA, 18, 5, (2011), 177-180. DOI: 10.3745/KIPSTA.2011.18.5.177.

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