Automated Synthesis of Moore and Mealy-model Time-stationary Controllers for Pipelined Data Path of Application Specific Integrated Circuits 


Vol. 2,  No. 2, pp. 254-263, Mar.  1995
10.3745/KIPSTE.1995.2.2.254


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  Abstract

In this paper we discuss Moore and Mealy-model Time-stationary control schemes of pipelined data paths of Application Specific Integrated Circuits (ASICs). We developed a method to synthesize both a Moore and a Mealy-style Finite State Machine (FSM) controller specifications given a pipelined data path with conditional branches. The control synthesis task consists of the generation of control specification and the FSM synthesis. The control specification procedure generates a FSM specification in the form of a state table. The different partitioning schemes are applied to each FSM controller so as to minimize the total area. Experimental results show the characteristics of the two different control styles and the effects of these two models on cost and performance.

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[IEEE Style]

K. J. Tae, "Automated Synthesis of Moore and Mealy-model Time-stationary Controllers for Pipelined Data Path of Application Specific Integrated Circuits," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 2, no. 2, pp. 254-263, 1995. DOI: 10.3745/KIPSTE.1995.2.2.254.

[ACM Style]

Kim Jong Tae. 1995. Automated Synthesis of Moore and Mealy-model Time-stationary Controllers for Pipelined Data Path of Application Specific Integrated Circuits. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 2, 2, (1995), 254-263. DOI: 10.3745/KIPSTE.1995.2.2.254.

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