Performance Analysis of n-way Set Associative Cache and Fully Associative Cache 


Vol. 4,  No. 3, pp. 802-810, Mar.  1997
10.3745/KIPSTE.1997.4.3.802


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  Abstract

In this paper, the performance of direct mapping caches, 2-, 4-, 8-, ..., 4096-way set associative caches, and fully associative caches are analyized by trace simulation for verifying their effectiveness. In general, it is well known that as n, the number of main memory lines to be stored into one cache line number in direct mapping cache, increases, the performance of the cache memory should get higher linearly. According to our analysis, however, it is not true on all the cache organizations. It is shown that as n increases, miss ratios get lower only when the small cache(less than 256K) using large line size is used. It is also shown that fully associative mapping achieves high performance only when small size cache using large line size is used.

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[IEEE Style]

C. Y. Hoon and K. J. Sun, "Performance Analysis of n-way Set Associative Cache and Fully Associative Cache," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 4, no. 3, pp. 802-810, 1997. DOI: 10.3745/KIPSTE.1997.4.3.802.

[ACM Style]

Cho Yong Hoon and Kim Jung Sun. 1997. Performance Analysis of n-way Set Associative Cache and Fully Associative Cache. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 4, 3, (1997), 802-810. DOI: 10.3745/KIPSTE.1997.4.3.802.

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