A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture 


Vol. 5,  No. 3, pp. 862-872, Mar.  1998
10.3745/KIPSTE.1998.5.3.862


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  Abstract

In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the accurate operation and effectiveness of the proposed architecture.

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[IEEE Style]

L. C. Hee, K. J. Hwan, Y. T. Jin, N. I. Gil, A. G. Seon, "A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture," The Transactions of the Korea Information Processing Society (1994 ~ 2000), vol. 5, no. 3, pp. 862-872, 1998. DOI: 10.3745/KIPSTE.1998.5.3.862.

[ACM Style]

Lee Chang Hee, Kim Jeong Hwan, Yun Tae Jin, Nam In Gil, and Ahn Gwang Seon. 1998. A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture. The Transactions of the Korea Information Processing Society (1994 ~ 2000), 5, 3, (1998), 862-872. DOI: 10.3745/KIPSTE.1998.5.3.862.

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