Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS 


Vol. 15,  No. 5, pp. 243-248, Oct.  2008
10.3745/KIPSTA.2008.15.5.243


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  Abstract

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35㎛ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

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[IEEE Style]

D. H. Kim and J. B. Kim, "Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS," The KIPS Transactions:PartA, vol. 15, no. 5, pp. 243-248, 2008. DOI: 10.3745/KIPSTA.2008.15.5.243.

[ACM Style]

Dong Hwi Kim and Jeong Beom Kim. 2008. Design of a Low-Power Carry Look-Ahead Adder Using Multi-Threshold Voltage CMOS. The KIPS Transactions:PartA, 15, 5, (2008), 243-248. DOI: 10.3745/KIPSTA.2008.15.5.243.

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