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A Study of Delay Test for Sequential Circuit based on Boundary Scan Architecture
Lee Chang Hee Kim Jeong Hwan Yun Tae Jin Nam In Gil Ahn Gwang Seon
Vol. 5, No. 3, pp. 862-872, Mar. 1998
10.3745/KIPSTE.1998.5.3.862
Vol. 5, No. 3, pp. 862-872, Mar. 1998
10.3745/KIPSTE.1998.5.3.862
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